An exemplary trench transistor of the field and a related method are disclosed in U.S. Pat. No. 5,814,858 A.
An important aim in the development of new generations of DMOS power transistors is reducing the on resistivity Ron·A. This makes it possible, on the one hand, to minimize the static power loss, and, on the other hand, it is possible to achieve higher current densities. Since the on resistance increases with the maximum drain voltage of a transistor, it is endeavored to manage with lower drain voltages. The specific capacitances responsible for the switching losses are only slightly dependent on the maximum drain voltage, thus resulting in smaller transistors with lower capacitances and lower switching losses.
Usually, for fabricating n-channel DMOS transistors, an n−-type epitaxial layer is deposited on a low-impedance n+-type substrate, the lower part of said epitaxial layer forming the drift path. The body region is produced by redoping the epitaxial region. In order to reduce the maximum drain voltage and the on resistivity of such a DMOS transistor, usually the drift path is doped more highly and the length of the drift path is simultaneously reduced. For a maximum drain voltage of less than approximately 20V, the doping of the drift path may become higher than the doping of the body region. However, the transistor can then no longer be fabricated according to the prior art because a reproducible redoping of the more highly doped epitaxial region is not possible.
In order to solve the above difficulties, there is a proposal, for realizing DMOS transistors having a relatively low maximum drain voltage, to deposit a p-type epitaxial layer on an n+-type substrate, said epitaxial layer forming the body region. The drain region is formed by the substrate. In this case, however, the thickness of the epitaxial region is controlled very imprecisely, and the outdiffusion of the substrate varies with the doping concentration thereof, with the result that the channel length is subjected to major fluctuations and the on resistance Ron of the transistor thus fluctuates greatly. Furthermore, there is the proposal to deposit a two-stage epitaxial layer, the bottommost layer of which is n-doped and the top layer of which is p-doped. In the above-mentioned US patent specification, for fabricating a low-voltage MOSFET trench transistor, in order to reduce the deviations of the breakdown voltage and of the on resistance that are caused by the thickness variations of the epitaxial layer, use is made of a high-energy implantation for definition of the drain region. However, in that case the junction between the epitaxial region and the substrate is defined by the implantation of a buried layer and an n-type epitaxial layer is used. Finally, in the US patent specification, high doses of 1×1014 cm−2 or more are required for implantation of the buried layer, with the result that the high implantation is not used for definition of the channel length. Furthermore, a certain thickness of the n-type epitaxial layer remains between the top side of the buried layer and the underside of the p-type body.
It would therefore be advantageous to specify a fabrication method for a trench transistor designed for a low maximum drain voltage and a trench transistor of this type in which it is possible to set more precisely the channel length by means of a high-energy implantation and also the doping of the drift region that forms the drain region.